The present invention relates to a semiconductor device, which includes a buried gate electrode and an isolation film and source/drain contacts that are self-aligned with the buried gate electrode, and also relates to a method for fabricating a device with such a structure.
Recently, the number of semiconductor devices that can be integrated on a single chip has increased by leaps and bounds as those devices have been tremendously downsized. As this miniaturization trend accelerates, a contact hole (or a contact formed by filling in the hole with a conductor), provided for interconnecting the gate electrode or doped layer of an MIS semiconductor device to an interconnection layer, has further reduced its size every time size generations alternate.
To reduce a margin needed in overlaying masks one upon the other during a photolithographic process and thereby further increase the number of semiconductor devices integrated, various methods for forming contacts self-aligned with a gate electrode have been researched and developed vigorously. Those contacts will be herein called xe2x80x9cself-aligned contactsxe2x80x9d. Hereinafter, a semiconductor device including the known self-aligned contacts and its fabrication process will be described.
FIG. 40 illustrates a cross section of a known MIS semiconductor device, including self-aligned contacts, taken in the channel direction (i.e., the gate length direction) thereof. As shown in FIG. 40, a trench isolation film 104 is provided on an Si substrate 101 and an MIS transistor is formed in an active region surrounded by the isolation film 104. The MIS transistor includes: a gate insulating film 105 of SiO2; a gate electrode 106 of polysilicon; an upper insulating film 107 of SiN; a nitride sidewall 109 of SiN; LDD regions 108; and heavily doped source/drain regions 110. The gate insulating film 105, gate electrode 106 and upper insulating film 107 are stacked in this order on the substrate 101 and the side faces of the gate electrode 106 and upper insulating film 107 are covered with the sidewall 109. The LDD regions 108 and heavily doped source/drain regions 110 are defined within the substrate 101 by introducing dopants thereto. Contacts 112 of tungsten, for example, are formed to pass through an interlevel dielectric film 111 over the substrate 101 and to reach the heavily doped source/drain regions 110. Depending on the direction of mask misalignment, these contacts 112 come into partial contact with the upper insulating film 107 and sidewall 109. And these contacts 112 are self-aligned contacts that have been aligned with the gate electrode 106 automatically.
FIGS. 41A through 41E are cross-sectional views illustrating respective process steps for fabricating the MIS semiconductor device including the known self-aligned contacts.
First, in the process step shown in FIG. 41A, a stopper insulating film 102, which may be a multilayer structure consisting of silicon dioxide and silicon nitride films, is deposited on an Si substrate 101. Then, parts of the stopper insulating film 102 and substrate 101, where the trench isolation will be formed, are etched to a predetermined depth, thereby forming a trench 103 in the substrate 101.
Next, in the process step shown in FIG. 41B, a CVD silicon dioxide film is deposited over the substrate and has its surface planarized by a chemical/mechanical polishing (CMP) process using the stopper insulating film 102 as a polish stopper. In this manner, the trench 103 is filled in with the CVD silicon dioxide film, thereby forming the trench isolation film 104. As a result, the upper surfaces of the isolation film 104 and stopper insulating film 102 are planarized to the same level. Once a desired planarity is attained, the stopper insulating film 102 is removed.
Then, in the process step shown in FIG. 41C, the exposed surface of the substrate 101 is thermally oxidized, thereby forming a gate insulating film 105 of SiO2. Subsequently, after polysilicon and silicon nitride film have been stacked in this order over the substrate, those two films are patterned by lithography and dry etching techniques to form a gate electrode 106 and an upper insulating film 107 in the active region. Thereafter, dopants ions are lightly implanted into the substrate 101 using the upper insulating film 107 and isolation film 104 as a mask, thereby defining LDD regions 108 self-aligned with the gate electrode 106.
Next, in the process step shown in FIG. 41D, a silicon nitride film is deposited over the substrate and then etched back, thereby forming a nitride sidewall 109 over the side faces of the upper insulating film 107 and gate electrode 106. Then, dopants ions are heavily implanted into the substrate 101 using the upper insulating film 107, sidewall 109 and isolation film 104 as a mask, thereby defining heavily doped source/drain regions 110 self-aligned with the gate electrode 106.
Subsequently, in the process step shown in FIG. 41E, a relatively thick CVD silicon dioxide film is deposited over the substrate and then planarized by a CMP process, thereby forming an interlevel dielectric film 111. Thereafter, contact holes, reaching the heavily doped source/drain regions 110, are opened through the interlevel dielectric film 111 and then filled in with a conductor, thereby forming source/drain contacts 112 that make electrical contact with the heavily doped source/drain regions 110.
According to this method, when the contact holes are opened through the interlevel dielectric film 111 so as to reach the heavily doped source/drain regions 110, the gate electrode 106 has already been covered with the SiN upper insulating film 107 and nitride sidewall 109. Thus, even if those holes are formed to overlap with the gate electrode 106 due to mask misalignment, the silicon nitride film serves as an etch stopper. As a result, the source/drain contacts 112 can be formed as self-aligned contacts without making the holes partially etch the gate electrode 106.
The semiconductor device with the known self-aligned contacts and its fabrication process, however, has the following drawbacks.
Firstly, in the known method of making the self-aligned contacts, the source/drain contacts must be formed within the contact holes that have been prepared by lithography and dry etching processes. Thus, the size of the source/drain contacts can be reduced to no smaller than the minimum opening size of a resist pattern for use in an exposure process.
The self-aligning technique for the known self-aligned contacts was developed to form the contact holes, reaching the source/drain regions, without getting the gate electrode etched even if those holes horizontally overlap with the gate electrode due to the placement error of photomasks for use in making the holes. This is because the upper and side faces of the gate electrode have already been covered with the silicon nitride film when those holes are opened. That is to say, this self-aligned contact making method was designed to increase an allowable mask overlay margin for a photolithographic process for forming the contact holes. Thus, the size of the contact holes themselves, in which the contacts should be formed by filling the holes with a conductor, is determined by the minimum opening size of a resist pattern.
FIG. 42A is a cross-sectional view illustrating an MIS transistor including the known self-aligned contacts along with the sizes of respective parts of the transistor. FIG. 42B is a plan view illustrating a photomask used for forming the contact holes.
As shown in FIG. 42A, the contact holes 114 reaching the heavily doped source/drain regions 110 are formed by etching the interlevel dielectric film 111 using a resist pattern 113 as a mask. Thus, it is impossible to reduce the size of the contact holes 114, in which the source/drain contacts should be formed, to less than the minimum opening size of the resist pattern 113 (i.e., a positive photoresist film in the illustrated example). The lower part 114a of the contact hole 114 on the left-hand side, located between the sidewall 109 and interlevel dielectric film 111, has a size smaller than the minimum opening size. However, this part 114a is formed due to the mask misalignment and this size is non-controllable. Accordingly, when a contact is formed inside the contact hole 114, the area of contact between the contact and heavily doped source/drain region 110 is smaller than the desired one. On the other hand, the upper part 114b of the contact hole 114 has a size approximately equal to the minimum opening size. Thus, it is virtually impossible to reduce the area of contact between the contact formed inside the contact hole 114 and an interconnection line, which will be formed on the contact, to less than the minimum opening size.
According to a normal exposure technique, the gate length determined by a resist pattern for a gate electrode (i.e., the length of the resultant gate electrode 106) may be equal to the minimum opening size (or the design rule in this case), e.g., 0.15 xcexcm. However, the resolution of a resist pattern with no line-and-space pattern, e.g., a resist pattern for making contact holes, is lower than that of a gate electrode pattern. Accordingly, openings with the minimum size of 0.15 xcexcm cannot be formed, and therefore the minimum opening size of the resist pattern 113 shown in FIG. 42A is about 0.2 xcexcm in a normal case. Thus, if the gate length of the gate electrode is defined at the minimum opening size, it is difficult to reduce the size of the source/drain contacts (or contact holes) to approximately equal to, or less than, the gate length in accordance with the currently available technique.
Secondly, the relative positional relationship among the gate electrode, isolation film and source/drain contacts is changeable depending on the mask overlay accuracy of an exposure system. Thus, an extra mask overlay margin is needed and the area of the active region cannot be reduced proportionally to a reduced design rule. And it is very difficult to further reduce the areas of the source/drain regions or the junction capacitance between the source/drain regions and substrate.
Usually, a photomask is designed in such a shape that the contact holes 114 will not overlap with the gate electrode 106 but will be located over the heavily doped source/drain regions 110 as shown in FIG. 42B. Suppose a semiconductor device has been formed by using such a photomask and by setting the mask overlay margin to zero and the gate length of the gate electrode 106 to the minimum opening size. In that case, the sizes of respective parts of the device as measured in the channel direction (i.e., the gate length direction) will be as shown in FIG. 42A. The gate length of the gate electrode 106 will be 0.15 xcexcm. The horizontal size of the sidewall 109 will be 0.12 xcexcm in total (i.e., 0.6 xcexcm each side). And the size of part of the source/drain regions 110 that is located between the sidewall 109 and isolation film 104 as measured in the gate length direction will be 0.4 xcexcm in total (i.e., 0.2 xcexcm each side). As described above, this size is approximately equal to the designed size of the contact holes 114. Add all of these sizes together, and the size of the entire active region interposed between the right- and left-hand side portions of the isolation film 104 will be about 0.67 xcexcm as measured in the gate length direction. The size of the active region except the gate electrode 106 with the length of 0.15 xcexcm will be about 0.52 xcexcm in total (i.e., 0.26 xcexcm each side) as measured in the gate length direction. The size of the heavily doped source/drain regions 110, including their parts diffused under the gate electrode 106, will also be about 0.52 xcexcm in total (i.e., 0.26 xcexcm each side) as measured in the gate length direction. On the other hand, supposing a mask overlay margin of about 0.01 xcexcm is needed in aligning each pair of parts with each other, the size of the entire active region will be about 0.75 xcexcm as measured in the gate length direction. Even if the design rule for a gate electrode, for example, has been reduced, this mask overlay margin does not decrease proportionally. Since it is expected that the design rule will be continuously reduced from now on, the mask overlay margin will constitute an increasingly great obstacle to downsizing of semiconductor devices.
According to the sizes specified above, the sizes of the active region and heavily doped source/drain regions as measured in the gate length direction are five or more times greater and four or more times greater than the gate length, respectively. Thus, it is necessary, but very difficult, to further reduce the sizes of the active region and heavily doped source/drain regions for the purpose of downsizing the semiconductor devices and reducing the junction capacitance.
Thirdly, in the conventional fabrication process, a gate electrode is formed by patterning and then LDD and heavily doped source/drain regions are defined. Thus, after the gate electrode has been formed, annealing should be performed to activate the dopants that have been introduced to define the LDD and source/drain regions. Accordingly, it is difficult to use a metal for the gate electrode and therefore the gate electrode is normally made of polysilicon or polycide with good thermal resistance. However, as the size of gate electrodes has been reduced, it has become increasingly hard to lower the resistance of the gate electrode made of polysilicon or polycide. Furthermore, when the gate electrode is made of polysilicon, boron, which has been introduced as a dopant, might diffuse from the polysilicon gate electrode through the gate insulating film into the channel region inside the substrate. As a result, the dopant concentration in the channel region and the threshold voltage of the device might change unintentionally.
To further downsize the semiconductor devices, the present invention adopts a completely new approach, which is totally different from the prior art.
An object of this invention is providing a downsized semiconductor device, of which the components can be freely disposed in an active region without being limited by the mask overlay margin, by self-aligning not only contacts but also an isolation film as well with a buried gate electrode.
Another object of this invention is providing a method for fabricating the device by this new self-aligning technique.
An inventive semiconductor device includes: a gate insulating film formed on a semiconductor substrate; a buried gate electrode formed on the gate insulating film; an upper insulating film formed on the buried gate electrode; a sidewall insulating film formed on side faces of the buried gate electrode and the upper insulating film; and a trench isolation film self-aligned with the buried gate electrode. The upper surface of the isolation film is located at a level higher than that of the buried gate electrode. The lower surface of the isolation film is located at a level lower than the upper surface of the substrate at least on a cross section of the device taken in a gate length direction. The device further includes: source/drain diffused regions defined in respective regions of the substrate beside the buried gate electrode; and source/drain contacts formed between the sidewall insulating film and the isolation film and self-aligned with the buried gate electrode to make electrical contact with the source/drain diffused regions.
In the inventive device, the upper surface of the trench isolation film is higher than that of the buried gate electrode and the source/drain contacts are interposed between the gate electrode and isolation film. In addition, since the source/drain contacts and isolation film are both self-aligned with the gate electrode, no mask overlay margin is needed. Thus the active region, surrounded by the isolation film, can have its size reduced in the gate length direction.
In one embodiment of the present invention, the gate electrode may be made of a metal. Then, a resultant MIS semiconductor device, including a buried gate electrode with low resistance, can exhibit high current drivability.
In another embodiment of the present invention, the gate insulating film may be formed out of a high dielectric constant insulating film with a dielectric constant higher than that of SiO2. In such an embodiment, even if the gate insulating film is thickened, the SiO2 converted thickness thereof (i.e., the thickness of an SiO2 film that has a capacitance equal to that of the gate insulating film) still can be reduced. As a result, the current drivability thereof improves and the leakage current, which usually increases when the gate insulating film is thinned, does not increase.
In still another embodiment, as viewed from over the device the source/drain contacts are preferably in substantially the same planar shape as the source/drain diffused regions in respective areas where the contacts overlap the source/drain diffused regions, and are preferably formed only over the source/drain diffused regions. Unlike the known source/drain contacts, which are formed by filling in contact holes with a conductor, the contacts can be made in any size. That is to say, the size of the source/drain contacts as measured in the gate length direction can be smaller than even the minimum opening size of a resist pattern. For example, the size of the source/drain contacts in the gate length direction may be in the range from 0.01 xcexcm to 0.1 xcexcm, for example.
In still another embodiment, the respective upper surfaces of the upper insulating film, the isolation film and the source/drain contacts are preferably planarized to substantially the same levels. In that case, the planarity of the substrate increases as a whole, thus improving the reliability of upper-level interconnects, for example.
In yet another embodiment, on a transversal cross section of the device taken across a part of the buried gate electrode, a periphery, outlining the sidewall insulating film, the buried gate electrode and the source/drain contacts, is preferably surrounded by the isolation film. Then, the isolation capability of the semiconductor device improves.
In yet another embodiment, the buried gate electrode in its entirety, including a gate contact region thereof, is preferably located only over the gate insulating film.
In this particular embodiment, on a transversal cross section of the device taken across a part of the buried gate electrode, a trench may be formed in the substrate around a periphery outlining the sidewall insulating film, the buried gate electrode and the source/drain contacts, and filled in with the isolation film.
In still another embodiment, on a cross section of the device taken in a gate width direction, the isolation film may be formed only over the upper surface of the substrate. And the device may further include a gate-width-defining trench isolation film, which reaches at least a region under a portion of the buried gate electrode where a gate contact will be formed on the cross section taken in the gate width direction. In such an embodiment, the channel region is sandwiched by the gate-width-defining trench isolation film, thus reducing the variation in electrical characteristics of the device.
In an alternative embodiment, the isolation film may include a gate-width-defining portion, which reaches at least a region under a portion of the buried gate electrode where a gate contact will be formed on a cross section taken in a gate width direction. And at least the lower surface of that portion of the buried gate electrode, where the gate contact will be formed, may be in contact with the gate-width-defining portion of the isolation film. Even in such an embodiment, the variation in electrical characteristics of the device can also be reduced.
An inventive method for fabricating a semiconductor device includes the steps of: a) forming at least a gate electrode dummy on a region of a semiconductor substrate where a buried gate electrode will be formed; b) forming a self-aligned sidewall film on side faces of the gate electrode dummy so that the sidewall film is self-aligned with the gate electrode dummy; c) depositing an insulating film over the substrate and removing part of the insulating film at least until the upper surfaces of the gate electrode dummy and the self-aligned sidewall film are exposed, thereby forming a trench isolation film; d) forming a gate hole, which exposes the substrate, by selectively removing the gate electrode dummy; e) forming a gate insulating film on the surface of the substrate, which is exposed inside the gate hole; f) forming the buried gate electrode on the gate insulating film by filling in the gate hole with a conductor; and g) defining source/drain diffused regions self-aligned with the buried gate electrode after the step a) has been performed.
According to the inventive method, the trench isolation film can be self-aligned with the buried gate electrode. Thus, the size of the active region, located between the gate electrode and isolation film, can be reduced in the gate length direction.
In one embodiment of the present invention, a trench is preferably formed in the step c) by etching the substrate to a predetermined depth using the gate electrode dummy and the self-aligned sidewall film as a mask, and then the isolation film is preferably formed by depositing the insulating film thereon. In this manner, the isolation capability of the isolation film can be improved in the resultant device.
In another embodiment, the inventive method may further include the steps of: h) selectively removing the self-aligned sidewall film after the step f) has been performed, thereby forming contact holes, which expose the substrate, beside the buried gate electrode; and i) filling in the contact holes with a contact material, thereby forming source/drain contacts. In this manner, source/drain contacts, self-aligned with the buried gate electrode, can be formed.
In this particular embodiment, the inventive method may further include the step of forming a sidewall insulating film on the side faces of the gate hole or the contact holes between the steps d) and i).
In an alternative embodiment, an insulating film, which will be shaped into the gate insulating film and a sidewall insulating film, may be formed in the step e) over the entire inner surfaces of the gate hole.
In still another embodiment, the inventive method may further include the step of forming a sidewall insulating film on the side faces of the gate electrode dummy between the steps a) and b).
In yet another embodiment, the step g) may be performed between the steps a) and b), and the self-aligned sidewall film may be used as source/drain contacts as it is.
In this particular embodiment, an insulating film, which will be shaped into the gate insulating film and a sidewall insulating film, may be formed in the step e) over the entire inner surfaces of the gate hole. In such an embodiment, there is no need to perform any thermal oxidation process and the process can be carried out at a relatively low temperature. Accordingly, the source/drain contacts can be formed out of a metal film with low resistance.
In yet another embodiment, a dummy upper passivation film may be formed in the step a) on the gate electrode dummy. In the step b), the self-aligned sidewall film may be formed on the side faces of the gate electrode dummy and the dummy upper passivation film. And in the step c), the insulating film and the dummy upper passivation film may be removed until the upper surface of the gate electrode dummy is exposed. In this manner, the self-aligned sidewall film can be formed in a good shape. Accordingly, whether this self-aligned sidewall film is used as the source/drain contacts themselves or as a dummy for the contacts, the reliability of the device improves.
In still another embodiment, the respective upper surfaces faces of the gate electrode dummy, the self-aligned sidewall film and the isolation film may be planarized in the step c) to substantially the same levels by a CMP process.
In yet another embodiment, a metal may be filled as the conductor in the step f). In such an embodiment, the resultant MIS semiconductor device, including a buried gate electrode with low resistance, has increased current drivability.
In yet another embodiment, a high dielectric constant insulating film with a dielectric constant higher than that of SiO2 may be formed in the step e) as the gate insulating film. In such an embodiment, the resultant semiconductor device will have higher current drivability and smaller gate leakage current.
In yet another embodiment, the inventive method may further include the step of forming a gate-width-defining trench isolation film in the substrate before the step a) is performed. In such an embodiment, the variation in electrical characteristics of the device can be suppressed.
In yet another embodiment, the inventive method may further include the steps of: removing both ends of the gate electrode dummy and the self-aligned sidewall film in a gate width direction between the steps b) and c); and etching away at least part of the isolation film, where a gate contact will be formed for the buried gate electrode, to substantially the same level as the upper surface of the substrate after the step d) has been performed. In such an embodiment, the variation in electrical characteristics of the device can also be suppressed.